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PRODID:-//Department of Electrical and Computer Engineering (HKUECE) 電機與計算機工程系 - ECPv6.15.20//NONSGML v1.0//EN
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X-ORIGINAL-URL:https://ece.hku.hk
X-WR-CALDESC:Events for Department of Electrical and Computer Engineering (HKUECE) 電機與計算機工程系
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TZID:Asia/Hong_Kong
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TZOFFSETFROM:+0800
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DTSTART:20240101T000000
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DTSTART;TZID=Asia/Hong_Kong:20250429T110000
DTEND;TZID=Asia/Hong_Kong:20250429T120000
DTSTAMP:20260509T211616
CREATED:20250424T014238Z
LAST-MODIFIED:20250424T014321Z
UID:111218-1745924400-1745928000@ece.hku.hk
SUMMARY:EEE MasterClass (EEE 大師講堂) – III-V Compounds on Si – Combining the Best of Both Worlds
DESCRIPTION:Abstract\nGaAs/InP and related alloys\, and III-nitrides are used for most high-performance device applications except CMOS logic. Optoeletronics\, high frequency (RF to THz) and power electronics are dominated by III-V compound semiconductors. We will discuss various factors of nature\, nurture\, and culture leading to today’s landscape. Photonic integrated circuits made with compound semiconductors on native substrates are costly and limited in wafer size and throughput. There is no universal formula for combining the best of both worlds –high performance and specific functionality of compound semiconductors with the efficiency and cost-effectiveness of Si integrated circuit manufacturability. Over the years\, intense efforts have been made to incorporate high-performance III-V active devices on silicon\, to be integrated with passive components and waveguides of Si photonics. Heterogeneous integration techniques such as wafer bonding and die bonding (transfer printing) have been developed for this purpose. We have used such approaches to demonstrate and commercialize high-resolution micro-LED micro-displays. To efficiently couple light between active and passive components for Si photonics\, we recently developed a unique growth scheme – Lateral Aspect Ratio Trapping” (LART) to enable lateral selective epitaxy of device quality III-V materials right on top of the buried oxide layer of patterned silicon-on-insulator (SOI) wafers by metal organic chemical vapor deposition (MOCVD). For fully vertical GaN trench MOSs grown on Si\, balancing all the tradeoffs in terms of device structure\, performance\, process complexity and throughput is being considered. \nSpeaker\nProf. Kei May LAU\nHong Kong University of Science & Technology \nBiography of the Speaker\nKei May LAU is a Research Professor at the Hong Kong University of Science & Technology (HKUST). She received her degrees from the University of Minnesota and Rice University and served as a faculty member at the University of Massachusetts/Amherst before joining HKUST in 2000. Lau is an elected member of the US National Academy of Engineering\, a Fellow of IEEE\, Optica (formerly OSA)\, and the Hong Kong Academy of Engineering Sciences. She was also a recipient of the IPRM award\, IET J J Thomson medal for Electronics\, Optica Nick Holonyak Jr. Award\, IEEE Photonics Society Aron Kressel Award\, and Hong Kong Croucher Senior Research Fellowship. She was an Editor of the IEEE Transactions on Electron Devices and Electron Device Letters\, and an Associate Editor for the Journal of Crystal Growth and Applied Physics Letters. \nOrganiser\nProf. Han WANG\nProfessor & Associate Head (New Initiative)\,\nDepartment of Electrical and Electronic Engineering\,\nThe University of Hong Kong \nAll are welcome!
URL:https://ece.hku.hk/events/20250429-1/
LOCATION:Tam Wing Fan Innovation Wing Two\, G/F\, Run Run Shaw Building\, The University of Hong Kong
CATEGORIES:Highlights,Seminar
ATTACH;FMTTYPE=image/jpeg:https://ece.hku.hk/wp-content/uploads/2025/04/1280-4.jpg
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