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X-WR-CALNAME:Department of Electrical and Computer Engineering (HKUECE) 電機與計算機工程系
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X-WR-CALDESC:Events for Department of Electrical and Computer Engineering (HKUECE) 電機與計算機工程系
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TZID:Asia/Hong_Kong
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DTSTART:20240101T000000
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DTSTART;TZID=Asia/Hong_Kong:20250912T150000
DTEND;TZID=Asia/Hong_Kong:20250912T160000
DTSTAMP:20260511T191720
CREATED:20250908T091544Z
LAST-MODIFIED:20250908T091544Z
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SUMMARY:RPG Seminar – Fully Integrated Memristive Spiking Neural Network with Analog Neurons for High-Speed Event-Based Data Processing
DESCRIPTION:Zoom Link: https://hku.zoom.us/j/99645936669 \nAbstract\nThe demand for edge artificial intelligence to process event-based\, complex data calls for hardware beyond conventional digital\, von-Neumann architectures. Neuromorphic computing\, using spiking neural networks (SNNs) with emerging memristors\, is a promising solution\, but existing systems often discard temporal information\, demonstrate non-competitive accuracy\, or rely on neuron designs with large capacitors that limit the scalability and processing speed. Here we experimentally demonstrate a fully integrated memristive SNN with a 128×24 memristor array integrated on a CMOS chip and custom-designed analog neurons\, achieving high-speed\, energy-efficient event-driven processing of accelerated spatiotemporal spike signals with high computational fidelity. This is achieved through a proportional time-scaling property of the analog neurons\, which allows them to use only compact on-chip capacitors and train directly on the spatiotemporal data without special encoding by backpropagation through surrogate gradient\, thus overcoming the speed\, scalability and accuracy limitations of previous designs. We experimentally validated our hardware using the DVS128 Gesture dataset\, accelerating each sample 50\,000-fold to a 30 µs duration. The system achieves an experimental accuracy of 93.06% with a measured energy efficiency of 101.05 TSOPS/W. We project significant future efficiency gains by leveraging picosecond-width spikes and advanced fabrication nodes. By decoupling the hardware’s operational timescale from the data’s natural timescale\, this work establishes a viable pathway for developing neuromorphic processors capable of high-throughput analysis\, critical for rapid-response edge computing applications like high-speed analysis of buffered sensor data or ultra-fast in-sensor machine vision. \nSpeaker\nSpeaker: Mr Zhu Wang\nDepartment of Electrical and Electronic Engineering\nThe University of Hong Kong \nBiography of the Speaker\nZhu Wang received the B.Eng. degree in the Department of Electronic Science and Technology at Harbin Institute of Technology\, and M.Phil. degree in the Department of Electronic Engineering at City University of Hong Kong. He is currently pursuing the Ph.D. degree in the Department of Electrical and Electronic Engineering at the University of Hong Kong\, under the supervision of Prof. Can Li. His research interests include AI chips\, neuromorphic computing\, memory\, and VLSI design. \nOrganiser\nProf. Can Li\nDepartment of Electrical and Electronic Engineering\, The University of Hong Kong \nAll are welcome.
URL:https://ece.hku.hk/events/20250912-1/
LOCATION:Online via Zoom
CATEGORIES:Seminar
ATTACH;FMTTYPE=image/jpeg:https://ece.hku.hk/wp-content/uploads/2024/11/rpg-seminar.jpg
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