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TZID:Asia/Hong_Kong
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DTSTART:20240101T000000
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DTSTART;TZID=Asia/Hong_Kong:20251114T140000
DTEND;TZID=Asia/Hong_Kong:20251114T150000
DTSTAMP:20260511T154000
CREATED:20251112T031147Z
LAST-MODIFIED:20251112T031147Z
UID:113872-1763128800-1763132400@ece.hku.hk
SUMMARY:RPG Seminar – A Hardware-Software Design Framework for SpMV Acceleration with Flexible Access Pattern Portfolio
DESCRIPTION:Zoom Link: https://hku.zoom.us/j/94562380867?pwd=ZLNMv8JgAFFrSAEfnTpb6iwdFC1p3E.1 \nAbstract\nSparse matrix-vector multiplications (SpMV) are notoriously challenging to accelerate due to their highly irregular data access pattern. Although a fully customized static accel- erator design may be adequate for small problems that can fit entirely within an on-chip memory buffer\, practical SpMV problems are large and have dynamic matrix structures that cannot easily be optimized at compile time. To address this need for trade-off between flexibility and performance\, we present SPASM\, a hardware-software framework that accelerates SpMV computation using a customizable portfolio of data access pat- terns as templates and a reconfigurable hardware to support their run-time execution. SPASM extracts local data access patterns of the input matrices and derives a set of template patterns to encode these inputs. Subsequently\, a novel hardware computing structure is proposed to support vectorized computation and flexible switching between different template patterns for each tile computation. Furthermore\, SPASM leverages the global compositions of input matrices to derive hardware configuration and workload schedules that improve load balancing among the parallel processing units. Importantly\, although SPASM can optimize the pattern portfolio for a particular set of expected input matrices\, the generated hardware can flexibly be used to accelerate SpMV of different input patterns albeit with reduced performance. Experimental results show that SPASM can achieve an average 2.81× speedup compared to the state-of-the-art SpMV accelerator while keeping a relatively low customization cost. \nSpeaker\nMr. Zhenyu Wu\nDepartment of Electrical and Electronic Engineering\nThe University of Hong Kong \nBiography of the Speaker\nZhenyu Wu received his B.Eng from Beijing Institute of Technology in 2021. He is now a PhD student from the Department of Electronic and Electrical Engineering\, the University of Hong Kong. He is supervised by Prof. Hayden Kwok-Hay So. His research interests include domain-specific accelerator design and sparse tensor algebra. \nOrganiser\nProf. Hayden Kwok-Hay So\nDepartment of Electrical and Electronic Engineering\, The University of Hong Kong \nAll are welcome.
URL:https://ece.hku.hk/events/20251114-1/
LOCATION:Online via Zoom
CATEGORIES:Seminar
ATTACH;FMTTYPE=image/jpeg:https://ece.hku.hk/wp-content/uploads/2024/11/rpg-seminar.jpg
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